Master Thesis in Exploring Deployment Optimizations towards HW/SW Codesign - remote possible

Neural networks (NNs) are commonly used in wide variety of applications. Since NNs exhibit enormous computational demands, deploying these neural networks on the edge or embedded platform offers various optimization opportunities. To embrace hardware diversity, it is important to map the neural network on HW efficiently. It involves exploring graph-level intermediate representation in various neural network compilers such as TVM, IREE etc. towards HW/SW codesign framework.

• During your thesis you will join our international team of researchers and engineers and contribute to the exploration of hardware-based optimization for AI acceleration.
• You will conduct literature research on state-of-the-art NN deployment optimization strategies. You will evaluate related work in terms of its suitability for an overarching interaction between efficient HW/SW codesign.
• Furthermore, you will investigate, evaluate, and optimize NN deployment methods and compiler tool stack particularly focusing on graph optimizations and strategies such as e.g. operation fusion or reordering.
• You will implement your solution in our torch framework and evaluate it in extensive simulations.
• Finally, you will document and discuss the results.

• Education: Master studies in the field of Electrical Engineering, Computer Science or comparable
• Experience and Knowledge: strong experience in Python/C++, neural network compiler (TVM), basic hardware knowledge, Deep Learning Concepts, Linux, LaTeX
• Personality and Working Practice: you excel at working independently, organizing tasks effectively, and staying highly motivated to achieve your goals
• Work Routine: mobile working within Germany
• Languages: good in English